1. Technical Field
The present invention relates in general to an improved data processing system, and in particular to an improved method and system for super-fast updating and reading of content addressable memory. More particularly, the present invention relates to an improved method and system for updating and reading content addressable memory with a bypass circuit for providing a fast update and read path.
2. Description of the Related Art
In a typical microprocessor, instructions are executed in a serial fashion. That is, a stream of instructions is executed by the microprocessor in the order in which the instructions are received. While this method of execution is effective, in many cases this method is not optimal because often many instruction sequences in a computer program are independent of other instruction sequences. Therefore, independent instructions may be executed in parallel to optimize performance. It is this concept of executing instructions in parallel, out-of-order, which underlies the executing methods of superscalar processors.
To provide for out-of-order execution, superscalar processors typically utilize more physical registers than available logical registers. Logical registers are registers which are referenced in the instructions. Physical registers are the registers within the processor which are actually used for storing data during processing. The extra physical registers are needed in superscalar processors in order to accommodate out-of-order, parallel processing. One consequence of having more physical registers than logical registers is that there is not one-to-one correspondence between the logical and physical registers. Rather, a physical register may correspond to a first logical register for one set of instructions and then correspond to second logical register for another set of instructions. Because the relationship between logical and physical registers can change, a mapping or coordination function is performed in order to keep track of the changing relationships.
This mapping may be performed utilizing a register map to locate the physical registers that hold the latest results for each logical register. In particular, a content addressable memory (CAM) array may be utilized as the register mapping tool in conjunction with other logic devices. The CAM array stores mapping data in CAM latches. The mapping data indicates, for each logical register, the respective physical register mapped thereto. When a logical register identifier is input to the CAM for an instruction, the mapping data from the latches is compared to the logical register identifier by compare circuitry. If a match occurs, the CAM asserts a match line indicating which physical register corresponds to the identified logical register. When a physical register is reassigned from one logical register to another, the mapping data in the CAM latches must be updated such that correct comparisons may continue.
As the number of instructions executed in parallel increases, the number of logical registers utilized and therefore the number of physical registers needed, increases. Further, the memory space required to implement a CAM array to map the logical and physical registers and make comparisons increases. Therefore, as processors increase in performance and capacity, an efficient method and system for performing register mapping, and in particular CAM accesses/updates during register mapping, is needed.
It is therefore one object of the present invention to provide an improved data processing system.
It is another object of the present invention to provide an improved method and system for super-fast updating and reading of content addressable memory.
It is yet another object of the present invention to provide an improved method and system for updating and reading content addressable memory with a bypass circuit for providing a fast update and read path.
The foregoing objects are achieved as is now described. The method and system provided may be utilized to efficiently perform register mapping in a superscalar processor, wherein a content addressable memory array stores mapping data which indicates the relationship between selected logical registers and associated physical registers and wherein compare circuitry compares the mapping data with a logical register identifier to identify the related physical register. The content addressable memory is updated with new mapping data while concurrently driving the new mapping data along a bus to compare circuitry. The new mapping data is compared with a logical register identifier in the compare circuitry, such that for instruction dispatch cycles which require updating and reading the content addressable memory, the new mapping data is dynamically written through to the compare circuitry during the update of the content addressable memory.